-16 (of 16) - 6. Future Work 7. Conclusions

A large potential to accelerate scientific algorithms lies in a hardware structure, which is a direct match to the structure of the algorithm. The MoM-3 is a universal accelerating co-processor, which can be configured to implement performace critical parts of an algorithm directly in hardware. The MoM-3 architecture supports fine grain parallelism by use of a highly reconfigurable ALU (rALU), and the increase of the effective memory bandwidth by avoiding addressing overhead. This is achieved by novel hardware concepts based on a new machine paradigm, which uses (one or more) data sequencers instead of an instruction sequencer. The operation principles of the MoM-3 are illustrated by a computationally intensive FIR filtering example. Compared a high-end SPARC station, actual speed-up factors between 12 and 62 (corresponding to technologically normalized speed-ups between 24 and 189) have been obtained for FIR filter and JPEG image compression algorithms.